The present invention relates to the fabrication of field effect transistor devices in which an insulated gate electrode is used to control an electric field in a semiconductor intermediate region between two more highly doped source/drain regions.
A significant problem faced recently in the semiconductor industry is the control of short channel effects in nanoscale transistor devices. As a consequence of the reduced control exerted by gate electrodes over carriers in an inversion channel beneath the gate electrode, there may be a significant degradation of sub-threshold slope in the high longitudinal field resulting from the drain to source voltage VDS, and a consequent increase in off-state current. High off-state current is undesirable since it reduces the ability to control the transistor using the gate electrode and increases total static power consumption.
In a conventional bulk MOSFET device, the off-state current is represented by a thermal diffusion current over a potential barrier and, therefore, the Fermi-Dirac distribution of carriers in any case limits the minimum sub-threshold slope to the well-known value of 60 mV/decade. This ultimately provides a limitation on switching speed of the transistor even if short channel effects are perfectly controlled.
Therefore, there has been considerable interest in alternative devices based on different transport mechanisms where the intrinsic 60 mV/decade limit can be overcome. These alternative devices include tunnel devices and impact ionization devices which have a high degree of compatibility with conventional CMOS fabrication processes.